2-15 years Relevant experience in Micro-architecture specification, implement logic functions in RTL using Verilog/System Verilog Qualifications Bachelors/Masters degree in electrical/electronics engineering/equivalent experience in ASIC/FPGA design Good knowledge of digital logic design, IP/SoC architecture and microarchitecture Experience with RTL tools/flows like Design Compiler, CDC (Clock Domain Crossing), Closing Timing Violations, reports analysis Good problem solving and analytical skills Ability to work in a dynamic environment Excellent communication skills, highly motivated and team player Experience with high-speed designs

1-15 years Relevant experience in in System Verilog, UVM, C++, Perl, Python. Good understanding of Logic Design and Architecture. Expertise in industry-standard verification flows like SV random testing, UVM, FV, coverage metrics, profiling tools, X prop, etc. Exposure on block level and system-level verification. Strong coding skills in System Verilog, scripting languages (Perl/python) and C++. Ability to collaborate and work with multiple groups. Prior experience in implementing Test plans for pre-silicon platforms. Understanding of DFT/IST is optional.

1-15 years Relevant experience in all aspects of DFT in top notch Switch products: DFT architecture and Testability strategy, Flow, Implementation, Verification and post Si bring up What We Need To See Very good knowledge on SCAN/ATPG/JTAG/MBIST Proven experience on gate level simulations with notiming and SDF based simulations for DfT modes Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques Proven experience in Scan insertion techniques at block level and Chip top level Good knowledge on Test mode timing constraints Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools) Good Knowledge and understanding on JTAG for IEEE1149.1/6 standards Experience with Post-Si ramp up and debug on ATE Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level Good knowledge on Perl/ Tcl scripting skills. Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project

1-15 years Relevant experience in synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management. An opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. Responsibility includes participating in or leading next generation physical design, methodology and flow development in advanced technology nodes Working closely with RTL design team & Analog Team to ensure successful tapeouts What We Need To See Experienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM. Successful track records of taping out complex IP’s & SoC’s at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus,Tempus, PVS, Voltus. Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl.

1-15 years Relevant experience in STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.Evaluate multiple timing methodologies/tools on different designs and technology nodes.Work on automation scripts within STA/PD tools for methodology development.Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus What We Need To See Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages – TCL, Perl, Awk Basic knowledge of device physics

1- 10 years Relevant experience in the design of PLLs, high speed SERDES, integrated filters, ADCs, DACs, and other analog building blocks What We Need To See Design and architect CMOS analog and mixed-signal integrated circuits Support Mixed-Signal IP through post-tapeout phase, including lab testing, customer bring-up and debug Ownership of circuit and system specifications Simulate designs with state-of-the-art CAD tools Document designs and simulation results Experience with high-speed SERDES circuits Knowledge of layout issues Experience with circuit simulators (HSPICE, Spectre, etc) Experience with Cadence Design Environment is an asset Strong written and oral communication skills Ability to work in a team environment Innovative and creative thinker Ability to quickly ramp on new projects Working knowledge of PERL and UNIX shell scripting languages is an asset